Tag Archives: hardware security

In this talk, we present our voltage fault injection attack against the AMD Secure Processor (AMD-SP / PSP). The AMD-SP is an ARM core, embedded into modern AMD CPUs. It hosts the firmware implementing the SEV API and is a single point of failure for the SEV technology. Our attack allows us to deploy custom code on the AMD-SP on Zen 1, Zen 2 and Zen 3 CPUs. We present how our attack allows attackers to fully circumvent SEV’s protection guarantees. To the best of our knowledge, the presented attack cannot be mitigated and questions SEV’s security promises on all affected CPU generations.

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Within a span of just a few years, we have gone from completely trusting our hardware to realising that everything is broken and all our security guarantees are built on sand. Memory chips have fundamental (Rowhammer) flaws that allow attackers to modify data without accessing it and CPUs are full of side channels and transient execution problems that lead to information leakage across pretty much all security boundaries. Combined, these issues have led to a string of high-profile attacks. In this talk, I will discuss some of the developments in such attacks, mostly by means of the attacks in which our group was involved. Although the research was exciting, I will argue that the way we conduct security research on hardware is broken. The problem is that the interests of hardware manufacturers and academics do not align and this is bad for everyone.

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Abstract: Physically Unclonable Functions (PUF) are a class of hardware security primitives, constructed to exploit the intrinsic variations in the integrated circuit fabrication process to give each silicon chip a unique identifier, in other words, a hardware-based fingerprint. Their relatively simple architectures and small overheads can answer many of the security challenges facing computing devices especially those operating in energy-constrained and/or physically exposed environments. The first part of this talk provides a comprehensive overview on the design principles of physically unclonable functions and their main evaluation metrics. The second part explains why we need the PUF technology and how to use it to build robust defence mechanisms against emerging security threats, giving specific examples that includes secure cryptographic keys generation/storage, authentication protocols, anti-counterfeit design for integrated circuits (IC) and low-cost secure sensors. The final part outlines the outstanding security challenges facing PUF technology and their potential countermeasures, including mathematical modelling…

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The Spectre attacks have demonstrated the fundamental insecurity of current computer microarchitecture. The attacks use features like pipelining, out-of-order and speculation to extract arbitrary information about the memory contents of a process. A comprehensive formal microarchitectural model capable of representing the forms of out-of-order and speculative behavior that can meaningfully be implemented in a high performance pipelined architecture has not yet emerged. Such a model would be very useful, as it would allow the existence and non-existence of vulnerabilities, and soundness of countermeasures to be formally established. We present such a model targeting single core processors. The model is intentionally very general and provides an infrastructure to define models of real CPUs. It incorporates microarchitectural features that underpin all known Spectre vulnerabilities. We use the model to elucidate the security of existing and new vulnerabilities, as well as to formally analyze the effectiveness of proposed countermeasures. Specifically,we discover three new (potential) vulnerabilities, including a new variant of Spectre v4, a vulnerability on speculative fetching, and a vulnerability on out-of-order execution, and analyze the effectiveness of existing countermeasures including constant time and serializing instructions.

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